
module tb_comp_test;

logic clk, rstn;

LilyRiscv_top DUT (
    .clk (clk),
    .rstn(rstn)
);

// initial and reset
initial begin
	clk = 0;
	rstn = 0;
	#600;
	rstn = 1;
end

// system clock
initial begin
	forever begin
		#10;
		clk = ~clk;
	end
end

// stop simulation
initial begin
	#10_000;
	$display("*****************************");
	$display("tb_comp_test simulation over!");
	$display("*****************************");
	$finish;
end

endmodule: tb_comp_test